1. Field of the Invention
This invention relates generally to communications systems and, more particularly, to a method and apparatus for multi-PHY communication without an ATM bus master.
2. Description of the Related Art
Packet switching communications networks, such as asynchronous transfer mode (ATM) communication networks, are typically made up of a number of communication nodes coupled for communication over a set of high speed communication links. Such a communication network enables communication among a wide variety of communication devices, including video, voice, data and facsimile devices. The topology of such a communication network enables a variety of communication paths to be established between any two communication nodes in the network.
An ATM arrangement consists of a plurality of protocol layers. The lowest protocol layer, the physical layer (PHY) incorporates the transceiver functions specific to the type of communications channel being employed. For example, the PHY layer may implement a variety of protocols for communication over a transmission medium connecting two devices. Such protocols include wireless, optical fiber, T1, T2, T3, etc. Above the PHY layer is the ATM layer, which is adapted to receive digital data, grouped in packets or cells, from the PHY layer.
To define the electrical interface between the PHY layer and the ATM layer, a Universal Test & Operations Interface for ATM (UTOPIA) specification was developed. The use of a standard interface allows the use of the upper ATM layers independent of the specific PHY layer implementation. Specific details on the UTOPIA interface are defined in UTOPIA Specification Level 1, Version 2.01 (af-phy-0017.000) available from The ATM Forum of Mountain View, Calif.
The UTOPIA level 1 specification defines an 8-bit parallel, synchronous bus with flow control. Communication is conducted in a point-to-point arrangement, where one master and one slave communicate. To increase the capabilities of the UTOPIA Level 1 protocol, the UTOPIA Level 2, Version 1.0 (af-phy-0039.000) specification was developed. UTOPIA Level 2 broadened the width of the interface to allow 16 bits to be used (i.e., optional), added address lines, and enabled multiple PHY devices to be placed on a common bus (M-PHY). In the M-PHY arrangement, an ATM master controls the flow of data on the bus. All communication is conducted between the individual PHY devices and the ATM master. If data from one PHY device is destined for another of the PHY devices on the same bus, the ATM master communicates with the first device, buffers the data, and then initiates a separate transaction to transfer the buffered data to the other PHY device. Only one PHY device at a time is allowed to drive the data and signal lines, as dictated by the ATM master.
One limitation of the M-PHY arrangement is that there is no capability to allow direct communication between PHY devices on the same bus. To meet the requirements of the various ATM specifications, an ATM master is typically highly complex and expensive. This expense limits the application in which an M-PHY arrangement is useful.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.